Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!rutgers!iuvax!pur-ee!uiucdcs!uiucdcsm!grunwald From: grunwald@uiucdcsm.cs.uiuc.edu Newsgroups: comp.arch Subject: Re: OS co-processor ?? Message-ID: <3300010@uiucdcsm> Date: Fri, 9-Oct-87 11:44:00 EDT Article-I.D.: uiucdcsm.3300010 Posted: Fri Oct 9 11:44:00 1987 Date-Received: Mon, 12-Oct-87 04:33:54 EDT References: <2272@umn-cs.UUCP> Lines: 14 Nf-ID: #R:umn-cs.UUCP:2272:uiucdcsm:3300010:000:585 Nf-From: uiucdcsm.cs.uiuc.edu!grunwald Oct 9 10:44:00 1987 If I'm not mistaken, the Convex C-1 architecture has a PPU-like setup with 68000 based systems managing I/O & interrupt handling. Also, doesn't the Alliant FX have IOPs? Cybers have had PPUs built from barallel-processors for eons -- all I/O and context switching requests for Cybers was done by these. A local group (Computer Based Education research Lab -- a.k.a. PLATO) is building cyber-CPUs which use 68000s as PPUs. Even the lowly Intel 310 has a quasi-OS processor -- the ethernet board in our system manages the rlogin & telnet sessions, freeing the main CPU of interrupts.