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From: jerry@oliveb.UUCP (Jerry Aguirre)
Newsgroups: comp.unix.wizards,comp.arch
Subject: Re: Double-bit errors and ECC memory
Message-ID: <6847@oliveb.UUCP>
Date: Sun, 11-Oct-87 21:14:38 EDT
Article-I.D.: oliveb.6847
Posted: Sun Oct 11 21:14:38 1987
Date-Received: Tue, 13-Oct-87 01:02:49 EDT
References: <1184@itm.UUCP> <797@spar.SPAR.SLB.COM> <2891@phri.UUCP> <7319@steinmetz.steinmetz.UUCP> <8587@utzoo.UUCP>
Reply-To: jerry@oliveb.UUCP (Jerry Aguirre)
Organization: Olivetti ATC; Cupertino, Ca
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Xref: mnetor comp.unix.wizards:4838 comp.arch:2609

In article <8587@utzoo.UUCP> henry@utzoo.UUCP (Henry Spencer) writes:
>Clearly, what we need, urgently, is ECC on the damn memory chips.  There

The disadvantage is that this provides less protection.  Off chip ECC
protects against the total failure of the chip, not just the failure of
a bit or two.  If an address or output line fails you would never know
about it with on-chip ECC.

There is also a problem with how the memory chips are going to
communicate the ECC information to the CPU.  Not only does the chip have
to notify the CPU about both uncorrected and corrected errors but, at
least at the diagnostic level, you probably want to be able to
interagate the chip about the details of the error.  All this sounds
like more IO pins which are already at a premium.

On the other hand having both would be a real win.  With each chip
handling its own ECC you could have every bit of a word wrong and still
have it corrected.  Also it could be checking every memory location at
refresh time instead of waiting to find errors when they are accessed.
(And having multiple errors accumulate in infrequently accessed words.)
With a second level of correction the on-chip ECC could fail silently
and thus not require any extra pins.

				Jerry Aguirre