Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!amdcad!ames!ucbcad!ucbvax!sdcsvax!ucsdhub!jack!man!nu3b2!nusdhub!rwhite From: rwhite@nusdhub.UUCP (Robert C. White Jr.) Newsgroups: comp.lang.c Subject: Re: Intel && C (was: Passing (char *) NULL) Message-ID: <104@nusdhub.UUCP> Date: Tue, 22-Sep-87 19:21:48 EDT Article-I.D.: nusdhub.104 Posted: Tue Sep 22 19:21:48 1987 Date-Received: Wed, 30-Sep-87 04:32:58 EDT References: <166@qetzal.UUCP> <157@hobbes.UUCP> <875@bsu-cs.UUCP> <882@mcgill-vision.UUCP> Organization: National University, San Diego Lines: 65 Keywords: MSC,NULL segments Summary: Flat Address Space does have a real meaning. In article <882@mcgill-vision.UUCP>, mouse@mcgill-vision.UUCP (der Mouse) writes: > >>> [H]as anyone else noticed how C is being warped, [...] because ONE > >>> microprocessor manufacturer [Intel] couldn't see fit to provide a > >>> flat, linear address space? > > So, Ron, what *is* a "flat linear address space"? A "flat linear address space" is a particularly apt discription of exactly what INTEL does NOT provide. Because the Segmenting and segment registers used by the x86 family are the way they are, there are many valid segment-offset pairs which refer to the same actual mechanical place in memory. Consider this: The alignment types for a data in the x86 environment are : byte, word, dword, paragraph, and page. There is also a missing "seg" but we will get back to that later. Because of these alignments there is an intresting anomality in the INTEL structure. the very first byte of memory in an intel machine may only be reached by the segment/offset of 0/0, the 16th may be reached by 0/16 or 1/0 the 32nd may be reached by 0/32, 1/16, or 2/0. Until you are beyond the first 64k of memory each additional 16 bytes adds one the the number of POSSIBLE methods to reach that single byte. There is a platu of sorts after 64k that ends in the last 64k of memory with FFFFh/FFFFh being only reachable in that one form. The mathimatical model is in the form [in binary]: Segment 0000000000000000 Offset 0000000000000000 + ____________________ Address xxxxxxxxxxxxxxxxxxxx where would one consistantly apply a SINGLE zero (0) to this addition, so that a comparison of the result to zero is consistant? The problem is that the frame of refrence to to heaped with possible combinations for a single constant to do. Other systems [68000 for example, (or so I have been told)] do not have a bit overlap. There is one and only one way to get to a memory address because the segment and offsets align like follows: Segment: 0000000000000000 Offset: 0000000000000000 + ________________________________ Address xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx In this model there is an actual 32bit register which represents the address [the segment and offset are logical subparts of a whole register]. That one register may be set to a constant zero (0) and be true consistantly. The WHOLE address is a real quantity in this model, as opposed to the aggrate of two parts in the INTEL model. In this latter model the "segment portion" may be only a few bits long, instead of a full word, but the general idea remains the same. If you consider the "depth" to be the number of possible was of acheiving an address, the INTEL model is heaped prety deep in the middle while the other model is in fact "flat and linear" Rob ("so who asked you?") White.