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Path: utzoo!mnetor!uunet!husc6!rutgers!mcnc!xanth!kent
From: kent@xanth.UUCP (Kent Paul Dolan)
Newsgroups: comp.sys.amiga
Subject: Re: Chip RAM
Message-ID: <2719@xanth.UUCP>
Date: Sat, 10-Oct-87 14:36:06 EDT
Article-I.D.: xanth.2719
Posted: Sat Oct 10 14:36:06 1987
Date-Received: Mon, 12-Oct-87 18:46:24 EDT
References: <1821@gryphon.CTS.COM>
Reply-To: kent@xanth.UUCP (Kent Paul Dolan)
Organization: Old Dominion University, Norfolk Va.
Lines: 15
Keywords: 1/2 M, 1M, 4M, PAL's
Summary: What gives?


A while back, we were being told that, because the address pins for
chip ram addressers were time multiplexed, adding one wire (pin?) took
us from 0.5 meg to 2 meg of chip ram, and that there "wasn't" an
intermediate 1 meg position.  Two meg is a comfortable amount of chip
ram for the current screen resolution and depth; 1 meg is still pretty
skimpy, especially considering that it is shared with sound info and
disk decoding buffer space.

Now we're being told that 1 meg is the answer, and that two meg can't
be attained for technical reasons.  What gives?

Did someone finally find a way to split a pin in half?  ;-)

Kent, the man from xanth.