Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!bbn!rochester!rutgers!ames!sdcsvax!ucbvax!hplabs!sdcrdcf!trwrb!aero!coffee From: coffee@aero.ARPA (Peter C. Coffee) Newsgroups: comp.sys.intel,comp.sys.ibm.pc Subject: Re: Clock speed on those darn 80?87 chips ... Message-ID: <17429@aero.ARPA> Date: Fri, 18-Sep-87 19:58:54 EDT Article-I.D.: aero.17429 Posted: Fri Sep 18 19:58:54 1987 Date-Received: Sun, 20-Sep-87 11:36:58 EDT References: <454@hubcap.UUCP> <17263@aero.ARPA> <7385@steinmetz.steinmetz.UUCP> <17428@aero.ARPA> Reply-To: coffee@aero.UUCP (Peter C. Coffee) Distribution: na Organization: The Aerospace Corporation, El Segundo, CA Lines: 20 Keywords: 8087, 80287, et al those math processors .... Xref: mnetor comp.sys.intel:351 comp.sys.ibm.pc:7982 Munching... Let me abandon anecdote and go to the source. From Intel Doc.210920-002, p.4: "The 80287 can operate either directly from the CPU clock or with a dedicated clock. For operation with the CPU clock (CKM=0), the 80287 works at one-third the frequency of the system clock (i.e., for an 8 MHz 80286, the 16 MHz system clock is divided down to 5.3 MHz). The 80287 provides a capability to inter- nally divide the CPU clock by three to produce the required internal clock (33% duty cycle). To use a higher performance 80287..., an 8284A clock driver and appropriate crystal may be used to directly drive the 80287 with a 1/3 duty cycle on the CLK input (CKM=1)." This explains the picture on p.128 of the June 1987 Byte showing a MicroWay daughterboard with a 12 MHz crystal nestled up against an 80287. The CKM line, pin 39 if anyone cares, would appear to be being driven high, an option described on p.2 of the aforementioned Intel document: "a HIGH input will cause CLK to be used directly." OK, to this degree the decision to let the chip divide by three *was* an AT design decision, but it sure was imitated with enthusiasm...