Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!uunet!munnari!moncskermit!labtam!scott
From: scott@labtam.oz (Scott Colwell)
Newsgroups: comp.unix.wizards
Subject: Re: Double-bit errors and ECC memory
Message-ID: <407@labtam.oz>
Date: Thu, 17-Sep-87 00:30:23 EDT
Article-I.D.: labtam.407
Posted: Thu Sep 17 00:30:23 1987
Date-Received: Sun, 20-Sep-87 15:10:36 EDT
References: <1184@itm.UUCP> <797@spar.SPAR.SLB.COM> <2891@phri.UUCP>, <8587@utzoo.UUCP>
Organization: Labtam International Pty. Ltd., Melbourne, Australia
Lines: 31
Summary: chips with onboard ecc do exist

In article <8587@utzoo.UUCP>, henry@utzoo.UUCP (Henry Spencer) writes:
> Clearly, what we need, urgently, is ECC on the damn memory chips.  There
> have already been mutterings about this, but no commercial products as
> far as I know.

	Micron Technology of Boise Idaho have actually done this.

	parts are :-	MT41C001	1M by 1
			MT44C256	256k by 4
	They are available in all the usual packages and ras access times
(Trac) and have 'real-time on-chip error correction using a modified Hamming
code'.

	Internally they use a 16bit data word with 5 check bits and (16,21)
Hamming code. How they get this when the normal row size is 512 on 1M DRAMs,
I don't know but this does suggest that it does not scrub during refresh.
	The pinouts are the standard pinouts for these parts and the speeds
are very similar to the same specs for old NMOS DRAMS. This is a bit of a
problem for us 'cause we would like to have the faster Tcac times (25ns for
100ns part) that the new generation of CMOS parts from Mitsubishi, Hitachi,
TI etc offer. (Micron part Tcac 50ns for 100ns part).

	As usual for DRAM manufacturers Micron are loathe to tell you the
error rates for the part. (If your listening, I'd like to see it on the
data sheets guys.)

-- 
Scott Colwell			ACSnet:	scott@labtam.oz
Design Engineer			UUCP:	..uunet!munnari!labtam.oz!scott
Information Systems Division	ARPA:	scott%labtam.oz@UUNET.UU.NET
Labtam Ltd Melbourne, Australia PHONE:	+61-3-587-1444
D