Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!uunet!mcvax!cernvax!ethz!tve
From: tve@ethz.UUCP (Th. von Eicken)
Newsgroups: comp.arch
Subject: Re: RISC Survey Articles
Message-ID: <216@bernina.UUCP>
Date: Thu, 15-Oct-87 18:49:30 EDT
Article-I.D.: bernina.216
Posted: Thu Oct 15 18:49:30 1987
Date-Received: Sun, 18-Oct-87 21:36:59 EDT
References: <3119@sol.ARPA> <6457@apple.UUCP>
Reply-To: tve@bernina.UUCP (Th. von Eicken)
Organization: ETH Zuerich, Switzerland
Lines: 53

In article <6457@apple.UUCP> bcase@apple.UUCP (Brian Case) writes:
>I have a personal problem with Multinovic's article because it 
>confuses the Am29000 and the Am29300 family; all the features attributed
>to the Am29000 are actually features of the Am29300 (a totally different
>beast).
You're not alone out there.
Actually, he really talks 'bout the 29300, only table 2 incorrectly
reads "AMD29000".

But if that only were the only bug!

_ The MIPS-CO processor should be called MIPS-R2000 so that it doesn't get
  confused with the Stanford MIPS project.

_ ARM gets wrong features attributed quite often. It doesn't "resemble the
  Pyramid in the sense that it employs an extremely large number of
  registers". It definitely has NO instruction or data cache. It has no
  delayed branch as far as I can tell. The interesting point, that every
  instruction gets executed conditionally is not mentioned altogether.

_ The paragraphs on interlocks are questionnable: what are "stated software
  interlocks"? The software reorganization needed in MIPS, MIPS-X and
  MIPS-R2000 are quite different I think.
  Furthermore, how can others follow the "Berkeley lead (with RISC-II I
  suppose) by providing hardware interlocks" if RISC-II didn't have any
  because it doesn't need any?

_ The MIPS-R2000 pipeline is quoted for complexity, I think the 6 stage
  CRISP pipeline with the decoded I-cache in the middle and operand
  forwarding from virtually every stage to every other is somewhat more
  complex. (No good/bad judjement intended here ...)

_ The "squashed" branches in MIPS-X are also found (in a different disguise)
  in the ROMP which is not mentioned.

_ Some nice sentences are sprinkled all over the paper. For example
  "Multiprocessor performance can scale linearly with the number of
  processors" (ugh!) or "The instruction cache is reported to have
  a 96 percent hit ratio".

_ I like table 4 though. Converting Mhz into ns cycle times is fun! And
  what was the story about MIPS?

I'll stop here 'cause I'm tired. I just hope I didn't make too many
mistakes myself in here ... apologies if I did.

				Thorsten von Eicken
				Institute for Integrated Systems
				Fed. Inst. of Tech., Zurich, Switzerland

				tve@ethz.uucp
				...!mcvax!cernvax!ethz!tve
_