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From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: RISC Survey Articles
Message-ID: <18826@amdcad.AMD.COM>
Date: Wed, 21-Oct-87 22:33:32 EDT
Article-I.D.: amdcad.18826
Posted: Wed Oct 21 22:33:32 1987
Date-Received: Sat, 24-Oct-87 12:42:31 EDT
References: <0VTFpfy00Vs80TU29Z@andrew.cmu.edu>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 25

In article <0VTFpfy00Vs80TU29Z@andrew.cmu.edu> zs01+@andrew.cmu.edu (Zalman Stern) writes:
+-----
| In article <216@bernina.UUCP> tve@bernina.UUCP (Th. von Eicken) writes:
| >_ The "squashed" branches in MIPS-X are also found (in a different disguise)
| >  in the ROMP which is not mentioned.
| 
| How is this? I do not see the similarity between anything in the ROMP
| processor (the chip used in the IBM-RT) and the squashed branches discussed
| MIPS-X article in the proceedings of the IEEE 14th Annual International
| Symposium on Comp. Arch.. Could you point out what I am missing?
+-----

The ROMP processor has branch and branch-with-execute instructions.  The
branch-with-execute instructions are of the "normal" RISC delayed branch
type.  The branch instructions can be used if the compiler would
otherwise have to place a nop in the delayed-branch slot.

I guess you could look at the branch instructions as a type of
squashing, since the "delay" instruction would be executed only if the
branch failed, but isn't that backwards from the MIPS-X version?

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)