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From: lamaster@ames.arpa (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: register windows
Message-ID: <3188@ames.arpa>
Date: Thu, 22-Oct-87 11:33:24 EDT
Article-I.D.: ames.3188
Posted: Thu Oct 22 11:33:24 1987
Date-Received: Sun, 25-Oct-87 01:45:37 EDT
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP>
Reply-To: lamaster@ames.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 13
Keywords: register windows, interrupt latency

This may have come up before- if so, I missed it.  The Sept. 87 issue
of IEEE Computer has an article, one of whose authors is The Michael
Flynn, which examines certain aspects of RISC architectures.  The
simulations described are using rather simple benchmarks, so it would
be dangerous to generalize too much from the article, but register
windows don't seem to be a win even where expect them to do best:
the benchmarks were medium sized Pascal programs with lots of procedure
calls.  (Another part of the article is an examination of tradeoffs
between compact instructions to reduce instruction traffic, and
simpler instructions + instruction cache using the same chip area...)

Do any of the register window advocates have similar studies which
demonstrate a WIN for register windows?