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From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: register windows
Message-ID: <18831@amdcad.AMD.COM>
Date: Thu, 22-Oct-87 12:23:21 EST
Article-I.D.: amdcad.18831
Posted: Thu Oct 22 12:23:21 1987
Date-Received: Sun, 25-Oct-87 01:27:08 EST
References: <201@PT.CS.CMU.EDU> <933@cpocd2.UUCP>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 16
Keywords: register windows, interrupt latency

In article <933@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes:

	... good stuff about register windows deleted ...

|an easy counterexample to Donald's sweeping generalization).  Task switch is
|harder to do well, agreed, but it occurs about 1/100th as often as call/return.

Actually, we measure more like .5% - 1% procedure calls ( == 1% - 2%
call+return). Assuming 40ns cycles and ~100 - 200 context switches/sec, then
context switches are only 1/1000 to 1/4000 as often as call/return.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)