Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Instruction cache for AMD 29000
Message-ID: <18856@amdcad.AMD.COM>
Date: Sun, 25-Oct-87 20:45:29 EST
Article-I.D.: amdcad.18856
Posted: Sun Oct 25 20:45:29 1987
Date-Received: Tue, 27-Oct-87 05:53:56 EST
References: <443@root44.co.uk>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 28
Keywords: cache cpu mmu

In article <443@root44.co.uk> jgh@root.co.uk (Jeremy G Harris) writes:

| Could someone remind me of the arguments against caching in physical space?
| 
| I was thinking about how the 29000 really cries out for an i-cache and it
| hit me that, because of the onboard address translation, it could not be
| a virtual-address cache.

Actually, physical caches are the most "natural" and have the least
amount of design headaches.  Virtual caches are used on processors with
external MMUs to get around adding "wait-states" for translation, but
they have to be designed to overcome problems associated with:

	* context switch
		the cache must be flushed or process-id tags must be
		included.
		
	* aliasing
		Two virtual addresses may map to the same physical
		address; the cache must be prevented from caching both
		addresses to maintain consistancy. 

	* consistancy in multiprocessing implementations

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)