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From: bcase@apple.UUCP (Brian Case)
Newsgroups: comp.arch
Subject: Re: register windows
Message-ID: <6554@apple.UUCP>
Date: Mon, 26-Oct-87 15:40:04 EST
Article-I.D.: apple.6554
Posted: Mon Oct 26 15:40:04 1987
Date-Received: Wed, 28-Oct-87 19:37:24 EST
References: <201@PT.CS.CMU.EDU> <933@cpocd2.UUCP> <821@mips.UUCP> <18843@amdcad.AMD.COM>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc., Cupertino, USA
Lines: 29
Keywords: register windows, interrupt latency

In article <18843@amdcad.AMD.COM> tim@amdcad.AMD.COM (Tim Olson) writes:
> [[MIPS numbers]]
>			nroff		asl
>     load/store %	  28%		 30%
>     non-zero offset%	  88%		 80%
>
>Contrast this to the statistics gathered on the Am29000 simulator
>(register-windowed machine):
>
>			nroff		asm29k
>     load/store %	  16%		 16%
>     non-zero offset%	  9.0%		 9.2%
>
>Now, since MIPS didn't publish the input they used on these programs to
>derive their numbers, we obviously cannot perform a direct comparison.

Just out of curiosity, are these numbers static or dynamic?  I would
hope that they both represent dynamic measurements.

Another thing to notice is that the load/store operations incurred by
stack cache over-/under-flows are guaranteed to be serial in nature;
that is, they are going to be to/from sequential addresses and are thus
amenable to load-/store-multiple (i.e. burst-mode) operations.  It may
be that a majority of load/store operations in non-stack-cache machines
are also around procedure calls and would also be amenable to burst-mode
transfers.  However, since over-/under-flows are rare events in stack-
cache machines (at least on the Am29000), the effect may not be significant.
Do you MIPS Co./AMD guys have any data on sequential/non-sequential
load/store behavior?