Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!mit-eddie!ll-xn!ames!necntc!linus!philabs!micomvax!onfcanim!dave From: dave@onfcanim.UUCP (Dave Martindale) Newsgroups: comp.arch,comp.unix.wizards,comp.os.minix Subject: Re: pdp-11/55 Message-ID: <15417@onfcanim.UUCP> Date: Thu, 15-Oct-87 17:01:33 EST Article-I.D.: onfcanim.15417 Posted: Thu Oct 15 17:01:33 1987 Date-Received: Sat, 31-Oct-87 05:37:15 EST References: <1755@ncr-sd.SanDiego.NCR.COM> <275@usl> <29933@sun.uucp> <2949@phri.UUCP> Reply-To: dave@onfcanim.UUCP (Dave Martindale) Organization: National Film Board / Office national du film, Montreal Lines: 67 Xref: mnetor comp.arch:2734 comp.unix.wizards:5165 comp.os.minix:1958 In article <2949@phri.UUCP> roy@phri.UUCP (Roy Smith) writes: >In article <29933@sun.uucp> guy%gorodish@Sun.COM (Guy Harris) writes: >> a PDP-11/55 (which was an 11/45 with bipolar memory hung off a fast >> memory bus). > > As I remember, the 11/45 was capable of having a certain amount >(8kbytes?) of MOS or bipolar ram in place of some of the core. Anybody >ever have a 45 so equiped? Did it make much difference? From "PDP-11/45 Processor Handbook, 1973" (somewhat yellowed by now): The processor used in the 11/45, 11/50, and 11/55 actually had two data paths to memory. One went to the normal system Unibus, and the other was a dedicated data path that went only to the dedicated local memory controllers. On the 11/45, there were no solid-state memory controllers installed, so all accesses to memory went via the Unibus and the special path was unused. On the 11/55, there was 1 or 2 special memory controllers connected to this interface, via dedicated slots in the CPU backplane. (I think DEC called this special interface the FASTBUS). Each memory controller could have bipolar or MOS memory attached to it. The bipolar memory was 300 ns access time, and you always used 4 boards on a controller, which gave you 4kw (16-bit words). Mos memory was 450 ns access with 4kw per card, and a controller could have 1-4 MOS boards giving 4-16kw. Each controller was all bipolar or all MOS, but one controller could have bipolar and the other MOS, giving a maximum complement of 8kw bipolar, 32kw MOS, or 4k bipolar plus 16K MOS. (Of course, you could also put memory on the main Unibus, but access was slower). These controllers were dual-ported, so they watched both the CPU memory interface and the UNIBUS, allowing peripherals to have access to the memory transparently. It should have made a big difference in performance; the 11/45 was capable of executing simple instructions (register-register add, failed conditional branch, etc.) one every 300 ns, as fast at they could be fetched from bipolar memory. Compare this to something like a VAX 780, or the 800 ns or so necessary to get a word from Unibus memory. The only 11/55 I ever saw was used at Waterloo to run a programming lab where lots of undergrads edited text files and then submitted the output to the local HASP machine for compile and execute. It did handle quite a few users (60?) but the system didn't let them do much. The above description is actually a simplification; the solid-state memory controllers were actually dual-ported to a second unibus, called "unibus B", not the main unibus (unibus A) which connected to the peripherals and other memory. Normally, a simple jumper was used to short the two unibuses together, in which case they became a single bus and solid-state memory really was dual-ported with the main unibus. However, if you removed this jumper, you could connect unibus B to another CPU's unibus, allowing that processor dual-ported access to the solid-state memory. The main CPU contained a bus arbitrator only for unibus A, so whatever unibus B was connected to had to provide its own arbitrator (e.g. another CPU). The 11/45 had interlocked memory access instructions, so multi-processor semaphores were possible via the shared memory. Another piece of trivia, and the reason the /45 was my favourite model of the PDP-11: the Unibus arbitrator ran even when the CPU was halted - it was a separate piece of hardware. Thus, you could use the console switches to deposit cylinder and track addresses and a "read" command into a disc controller, and the data appeared in memory. No boot code was necessary. For other members of the family, the bus arbitrator ran only when microcode was executing, so you needed to be executing instructions (just branch-to-self would do) in order for DMA to memory to work.