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From: franka@mmintl.UUCP (Frank Adams)
Newsgroups: comp.arch
Subject: Horizontal pipelining
Message-ID: <2525@mmintl.UUCP>
Date: Wed, 28-Oct-87 16:06:55 EST
Article-I.D.: mmintl.2525
Posted: Wed Oct 28 16:06:55 1987
Date-Received: Thu, 5-Nov-87 07:16:54 EST
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU>
Reply-To: franka@mmintl.UUCP (Frank Adams)
Organization: Multimate International, E. Hartford, CT.
Lines: 26
Keywords: multiple users


[Not food]

I had an idea some time ago that I'm surprised I've never seen discussed.
Suppose, for example, that your instruction processor has four stages.  With
conventional pipelining, that means that four consecutive instructions from
the same program are at some stage of execution at the same time.

Instead, why not have four different execution threads being performed
simultaneously?  This eliminates the dependency checks and latency delays
inherent in "vertical" pipelining.  (Many RISCs put these into the compiler
instead of the architecture, but they're still there).  On a multi-user
system with a reasonable load level, it seems to me that this should
represent a performance improvement.  Of course, it won't look good on the
standard benchmarks.

One drawback I can see is that multiple register sets must be kept active
simultaneously.  However, this doesn't seem like a major problem given
current technology.

Has anyone tried anything like this?  Is there some major problem I'm
overlooking?
-- 

Frank Adams                           ihnp4!philabs!pwa-b!mmintl!franka
Ashton-Tate          52 Oakland Ave North         E. Hartford, CT 06108