Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!hplabs!pyramid!prls!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: RISC Message-ID: <863@winchester.UUCP> Date: Sun, 1-Nov-87 18:23:38 EST Article-I.D.: winchest.863 Posted: Sun Nov 1 18:23:38 1987 Date-Received: Thu, 5-Nov-87 21:51:07 EST References: <1656@geac.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 29 Keywords: RISC,array In article <1656@geac.UUCP> arnold@geac.UUCP writes: >I have been hearing a lot about this new Reduced Instruction Set C? >technology...well I understand that if you restrict yourself to a >small instruction set and run it fast you get faster compiled >programs (I guessed this was the assumption). But I have been unable >to find out just what the hardware differance is (though I have >heard referance to arrays?(I think that was it)). >So could someone out there explain a bit? Well, it's not really new [Seymour Cray has been designing RISCy machines for eons, the IBM 801 is well over 10 years old, and various folks (Pyramid, Ridge) have been selling RISC machines for a while.] The only really recent part is doing it in VLSI, and the ramifications thereof. There have been many discussions in this newsgroup, so rather than repeating them, how about just a few good references: 1) John Hennessy, "VLSI Processor Architecture", IEEE Trans on Computers, C-33, no 12, Dec 1984, 1221-1246. 2) David A. Paterson, "Reduced Instruction Set Computers", Comm. ACM 28, 1 (Jan 1985), 8-21. 3) George Radin, "The 801 Minicomputer", ACM SIGARCH 10, 2 (March 1982). -- -john mashey DISCLAIMER: UUCP: {ames,decwrl.prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086