Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!hplabs!pyramid!prls!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: RISC Message-ID: <864@winchester.UUCP> Date: Sun, 1-Nov-87 19:05:44 EST Article-I.D.: winchest.864 Posted: Sun Nov 1 19:05:44 1987 Date-Received: Thu, 5-Nov-87 21:51:32 EST References: <1656@geac.UUCP> <1710@charon.unm.edu> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 30 Keywords: RISC,array In article <1710@charon.unm.edu> collier@charon.UUCP (Uncia Uncia) writes: >i would be grateful if someone could provide a quicky review >of the MIPS pipeline. i have forgotten the details but if i >remember correctly it was very simple and elegant, so perhaps >it wouldn't take up too much of someone's time. See Moussouris, et al, "A CMOS RISC Processor with Integrated System Functions", Proc IEEE COMPCON, SanFrancsico, March 1986, 126-143, for the details. The integer unit is basically a 5-stage pipe: I-cache reference (instruction fetch) Register Fetch / Decode / next PC determination ALU / Address calculate Data-cache / memory access Write-back to register file IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB IF RD ALU MEM WB This is a simplification: some things happen on half-cycle boundaries, and virtual-physical translations are also happening in an overlapped fashion. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl.prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086