Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!sunybcs!boulder!hao!oddjob!mimsy!chris From: chris@mimsy.UUCP Newsgroups: comp.lang.misc Subject: Re: software ICs vs. libraries Message-ID: <9134@mimsy.UUCP> Date: Wed, 28-Oct-87 04:02:15 EST Article-I.D.: mimsy.9134 Posted: Wed Oct 28 04:02:15 1987 Date-Received: Sat, 31-Oct-87 01:31:07 EST References: <3405@ece-csc.UUCP> <638@its63b.ed.ac.uk> <1811@watcgl.waterloo.edu> <1270@csib.csi.UUCP> Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742 Lines: 49 In article <1270@csib.csi.UUCP> jwhitnel@csi.UUCP (Jerry Whitnell) writes: >1) Simplicity of function: [A software] IC should have one and only >one function. ... This relates directly to the hardware IC which implements >a single function (whether it is an AND or a Multiplexer). Like the 74158? If I recall correctly, this is a dual decade counter with latches and BCD-to-seven-segment decoder-and-drivers. In other words, it is like two 7490s, two latches (numbers forgotten), and two 744[78]s. (The point is that subroutines and hardware both come in simple and complex versions. There are a number of special-purpose 74xx ICs.) >2) Layered. Not only should the calling function interface be defined, but >also the called functions interfaces should be defined. ... A example of >where this concept is not used but should be is the UNIX malloc function. 7400 series chips are not layered, they are self-contained. I am not sure there is any suitable hardware analogue for subroutine layering. >3) Well documented. If you looks at a 7400 book, you can see the wealth of >information provided about ICs. On the other hand, much of the information is assumed (from the class of the hardware). This sounds familiar.... >4) Machine/OS/Language independent. For a hardware engineer, all of the >iterfaces are standard (TTL), ... and DTL and ECL and ... >as are the ICs (7400). ... and 5400 and (now I have forgotten the CMOS series numbers, 4800?) >This means that an engineer can mix and match with no worry about >the enviroment the final product will end up in. Different choices >can be made for reasons of costs, speed, power consumption all >without changing the base design. Not at all. Different classes of logic families with the same functions (such as changing all your TTL to CMOS so you can run off 3V or 15V) have different characteristics (e.g., fan-out). You cannot just renumber your design: you have to check everything all over again. I think that we can in fact do *better* with software than with hardware. -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7690) Domain: chris@mimsy.umd.edu Path: uunet!mimsy!chris