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From: mwm@VIOLET.BERKELEY.EDU (Mike  Meyer, My watch has windows)
Newsgroups: comp.sys.amiga
Subject: [hoptoad!gnu@ucbvax.berkeley.edu  (John Gilmore): Signetics (Philips) scc68070 CPU chip]
Message-ID: <8710221134.AA27961@violet.berkeley.edu>
Date: Thu, 22-Oct-87 07:34:37 EDT
Article-I.D.: violet.8710221134.AA27961
Posted: Thu Oct 22 07:34:37 1987
Date-Received: Sat, 24-Oct-87 21:50:05 EDT
Sender: daemon@ucbvax.BERKELEY.EDU
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I thought that the rest of you (especially those who complain about
that missing MMU) would like to see this.

Now you've got a drop-in for the 68K with an MMU. Now, all you need is
a new OS....

	<mike

------- Forwarded Message

Date: 22 Oct 87 08:48:24 GMT
From: hoptoad!gnu@ucbvax.berkeley.edu  (John Gilmore)
Subject: Signetics (Philips) scc68070 CPU chip
To: info-68k@ucbvax.Berkeley.EDU

I just looked over a preliminary data sheet for the 68070 tonight.
It's basically a 10 MHz 68000 with a crazed 'segment based' mmu, UART,
timers, DMA channel, kitchen sink, etc all on a CMOS chip in a small
plastic chip carrier.  It also has 68010 style bus errors (virtual memory)
and a CLR instruction that doesn't read its target.  Its memory bus
is the standard 68000/68010 4 clock cycle, with 24 address bits, 16 data
bits, but no function codes.  Interrupts are simpler but well designed.
I hear there are a bunch of second sources lined up.

However, for some reason just about EVERY instruction runs from 1 to 15
cycles SLOWER than the 68000!  All the simple instructions run in 7
cycles instead of 4; long math to registers 1 cycle slower, to memory 3
cycles slower; branches are 2 to 5 cycles slower; JSR 9 cycles slower.
Base/displacement addressing (e.g. stack references) is 3 cycles slower.
Even worse, MOVEM takes 7 cycles per short or 11 per long, meaning you
can't do block moves at memory bandwidth.  And DBRA is 7 cycles slower
when it loops.  All of the above is with the MMU turned off; if you turn
it on, you lose a wait state on each memory reference, too.

In fairness, byte, word, and long operations in registers now all take
the same amount of time, though all these times are still slower than
the 68000; and a very few instructions are faster (RTS).

Watching this puppy on a scope is going to show a lot of "dead time" on
the memory bus, like the 68000 never had.  They have clearly redesigned
the guts of the CPU; it looks almost like they are incrementing the PC
with the ALU.  Does anybody know why?  I thought Signetics was licensed
to produce the 68000; why didn't they just use the old one?  It wasn't
a 68020 but it was at least as fast as a 68000...
- -- 
{dasys1,ncoast,well,sun,ihnp4}!hoptoad!gnu			  gnu@toad.com

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