Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!gatech!bloom-beacon!mit-eddie!ll-xn!ames!ucbcad!ucbvax!unisoft!gethen!farren From: farren@gethen.UUCP Newsgroups: comp.sys.amiga Subject: Re: Monitor mishmash Message-ID: <272@gethen.UUCP> Date: Sat, 31-Oct-87 08:17:51 EST Article-I.D.: gethen.272 Posted: Sat Oct 31 08:17:51 1987 Date-Received: Tue, 3-Nov-87 00:39:26 EST References: <3113@ccicpg.UUCP> <4410014@hpcvcd.HP> <2671@cbmvax.UUCP> Reply-To: farren@gethen.UUCP (Michael J. Farren) Organization: Sci-Fido - Unix in Oakland Lines: 40 In article <2671@cbmvax.UUCP> hedley@cbmvax.UUCP (Hedley Davis) writes: >In article <4410014@hpcvcd.HP> charles@hpcvcd.HP (Charles Brown) writes: > >The bandwidth during the video time is 14.32 Mbits per bit per pixel. > ( four pixels per 3.58 mhz cycle in highres mode ) I assume you mean 14.32 Mbits/sec, instead of Mbits/bit. Other than that, you are mostly correct. Those four bits, though, are actually four bytes, read serially every 1.12 microseconds (four color clocks), and "written" to the screen, via the lookup tables and A/Ds, as eight pixels, each with twelve bits of color information. The net result is eight pixels written every 1.12 microseconds, or approximately 7.15 Megapixels/second (twice the color clock, or 140 ns/pixel). If you organize your scan converter ram as twelve parallel channels, one per bit of color information, then you only have to read one pixel every 140 ns. Use four-bit-wide RAM, and you only actually access the RAM every four pixels, therefore have 560 ns access time. You have to write them out at twice the rate, of course, so you actually have three pixels to deal with every 140 ns, which works out to a 186 ns access time, which is tight, but not unattainable with a little clever design. Use two four-bit-wide chips in parallel, and you lower your access time to 372 ns, and you can get away with 24 RAMs, each 64K X 4, at a total cost for RAMs of less than $75 when purchased in single quantities, and probably less than $50 in production quantity. This calculation done using 4464 chips, with pricing from Microprocessors Unlimited, not the cheapest supplier around. Other considerations, such as the cost of the shift registers, timing circuitry, A/Ds, and such will drive up the cost. This thing isn't going to be cheap, no matter how you do it. I figure a minimum manufacturing cost of $100 (probably optimistic), which translates to something around $400 retail cost. It'd make a good hacker's project, though - does C/A plan on selling prototyping boards for the video slot? -- ---------------- Michael J. Farren "... if the church put in half the time on covetousness unisoft!gethen!farren that it does on lust, this would be a better world ..." gethen!farren@lll-winken.arpa Garrison Keillor, "Lake Wobegon Days"