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Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!oliveb!amiga!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.atari.st,comp.sys.misc,comp.sys.amiga
Subject: Re: Atari Transputers ? & A British ST/Amiga Rival ?
Message-ID: <2473@cbmvax.UUCP>
Date: Mon, 12-Oct-87 14:36:49 EDT
Article-I.D.: cbmvax.2473
Posted: Mon Oct 12 14:36:49 1987
Date-Received: Wed, 14-Oct-87 06:00:21 EDT
References: <1717@bath63.ux63.bath.ac.uk>
Organization: Commodore Technology, West Chester, PA
Lines: 42
Xref: mnetor comp.sys.atari.st:5653 comp.sys.misc:927 comp.sys.amiga:9337

in article <1717@bath63.ux63.bath.ac.uk>, pes@ux63.bath.ac.uk (Smee) says:
> Xref: cbmvax comp.sys.atari.st:5398 comp.sys.misc:909 comp.sys.amiga:8944
> 
> The point of RISC chips is that they can go faster because they have fewer,
> *simpler* instructions.  It's based on the theory that the vast majority
> of instructions used (frequency of use in real code) are the simple ones,
> but they have to be slowed down and made tricky in order to accomodate the
> fancy high-powered instructions which the processors support (store multiple,
> move with edit, BCD math, etc...)  By restricting the set of instructions to
> only the simple ones, the processor can be clocked much faster (more MIPS).
> The complex thingies are then constructed in assembler from the simple
> instructions.

Actually, there's no reason why a complex CISC instruction should slow down
the simpler form of the same instruction.  There are a few reasons why CISC
machines of today execute instructions slower than RISC machines.  One factor
is that a CISC instruction is often built using microcode, while a RISC
instruction can be hard-wired in, since it is much simpler to implement.
If the chips run at the same speed, the CISC machine will probably win here,
since any one instruction gets more work done.

However, all of the RISC stuff really has one overriding factor that lets it
be faster per instruction that CISC, and that's the simplicity of the design.
If I have a design that can be built in 20,000 gates instead of 200,000 gates,
I can use a newer, faster IC technology.  So while I'm building CISC chips in
NMOS, I can take my new fast CMOS process and build the much smaller RISC
part.  When that CMOS process is mature enough to support the size of a 
CISC chip, I can build my RISC chip in the newer, faster submicron CMOS
process.  Once that process lets me build 200,000 gate chips, my yet even
faster GaAs (or whatever) may be mature enough to let me build RISC.

Of course you have to track the design of main memory along with all of this,
too.  Even if your RISC architecture can run 20 times the instruction rate
of your CISC, if there's no main memory to support this, the RISC may loose
big, since it needs to get more instructions executed per second to keep
up with the more work per instruction aspect of CISC.  So you get strange
new architectures that are loosely termed RISC, like load/store architectures,
on-chip RAM, lots of registers, etc.  
-- 
Dave Haynie     Commodore-Amiga    Usenet: {ihnp4|caip|rutgers}!cbmvax!daveh
   "The B2000 Guy"              PLINK : D-DAVE H             BIX   : hazy
    "Computers are what happen when you give up sleeping" - Iggy the Cat