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From: jkg@pyr.gatech.EDU (Jim Greenlee)
Newsgroups: comp.sys.m68k
Subject: DTACK*
Message-ID: <4215@pyr.gatech.EDU>
Date: Wed, 14-Oct-87 11:09:25 EDT
Article-I.D.: pyr.4215
Posted: Wed Oct 14 11:09:25 1987
Date-Received: Fri, 16-Oct-87 00:34:05 EDT
Reply-To: jkg@pyr.UUCP (Jim Greenlee)
Organization: Georgia Institute of Technology
Lines: 58

I have a basic fundamental (probably stupid) question about DTACK*. I was
told  (by a Motorola person) that it was possible to wire DTACK* directly
to ground and have a 68000 system run at full speed, provided the memory
access time was fast enough. This runs counter to my understanding of
how DTACK* works.

DTACK* is sampled at the falling edge between S4 and S5 during a 68000 bus
cycle. If it is found to be low (on read cycle), then the data is latched
by the 68000 on the falling edge between S6 and S7, and the bus cycle is
terminated. This would indicate that DTACK* is a level-sensitive input.

However, I have built a couple of home-brew 68000 systems, and have used
the DTACK* input as a simple hardware single-step mechanism. It is clear 
that only one bus cycle is executed per pulse of the DTACK* line. In this
instance (which is based on observation), DTACK* appears to be an edge-
sensitive input.

The 68000 hardware manual seems to contradict itself on this issue. For
instance on pages 4-6 and 4-7, (section 4.2.1.1) there are a couple of u
flowcharts that describe the handshaking operation between the 68000 and 
a slave device. In both cases, the it clearly shows that DTACK* is first 
asserted and then negated by the slave on each bus cycle. This supports 
the edge-sensitive model.

However, on page 4-23 (section 4.4), asynchronous operation is described
as follows:

   "Using this method, AS* signals the start of a bus cycle and the
    data strobes are used as a condition for valid data on a write
    cycle. The slave device (memory or peripheral) then responds by
    placing the requested data on the data bus for a read cycle or
    latching data on a write cycle and asserting the data transfer
    acknowledge signal (DTACK*) to terminate the bus cycle."

And then in the next paragraph:

   "The DTACK* signal is allowed to be asserted before the data from a
    slave device is valid on a read cycle."

The negation of DTACK* is not specifically mentioned, which would support
the level-sensitive model. 

The usual method of generating DTACK* for non-bus-compatible peripherals
is to delay the address or data strobes by means of a shift register and
then run that output back to the DTACK* input. This is what I have always
done, and it has always worked. Has anybody ever done a 68000 design where
they wired DTACK* directly to ground? Can anybody tell me absolutely if
it is level- or edge-sensitive? My experience tells me that DTACK* must
be clocked, otherwise my single-stepper would never have worked. However,
everybody that I've put this question to swears that it's level-sensitive.
Who's right?

						Jim Greenlee
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