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From: dam@mtgzz.UUCP (XMRN50000[sms]-d.a.morano)
Newsgroups: comp.sys.m68k
Subject: Re: DTACK*
Message-ID: <3173@mtgzz.UUCP>
Date: Fri, 16-Oct-87 19:38:51 EDT
Article-I.D.: mtgzz.3173
Posted: Fri Oct 16 19:38:51 1987
Date-Received: Sun, 18-Oct-87 06:09:49 EDT
References: <4215@pyr.gatech.EDU>
Organization: AT&T, Middletown NJ
Lines: 41
Summary: DTACK* level sensitive (long)


Concerning the DTACK* question, the 68K processor is just a big
synchronous state machine which finds out if asynchronous input signals 
have changed by sampling them as levels.  This is characteristic
of all purely synchronous state machines.  They find an edge by sampling 
the signal first at one level and later sampling it
at the other level ; an edge must have occurred between the two samples
in which the signal is seen at opposite levels.

From what I can read in the manuals,
DTACK* is sampled starting from the -falling- edge of S4 and continues to
be sampled at every falling edge after S4 until it is seen to be asserted.
After a sample is seen in which DTACK* is asserted, the processor
waits one full clock and then negates AS* and DS* which also occurs
on a falling edge.

If DTACK* remains asserted after AS* and DS* is negated, the processor
doesn't mind and instead proceeds with its business.  If DTACK* remains
asserted from one bus cycle into the next up to the falling edge of
S4, then the processor will simply wait a clock and end the cycle
normally as before (with the effect of no wait states).  Although
I have not ever tried grounding DTACK*, I have been told by my local
Motorola application engineer that there is no problem with that arrangement.
Note that this is usually not a wise action since there is usually a
slow peripheral like a UART or some thing similar that would have to
be fairly fast if DTACK* were always grounded.

The choice of S4 above holds for the '008, '000, '010, and '012.
For the '020, replace S4 with S2.  The choice of S4 is exactly what
gave the original versions the minimum 4 clock cycle.  The choice of
S2 for the '020 is what allows it to have a minimum bus cycle of 3 clocks.

All of the above processors wait one clock before acting on an 
asserted DTACK* because it is actually pre-sampling the signal internally.  
This is done to avoid a meta-stable which is dissasterous to a state 
machine that makes a decision based on an input which may result in the 
change of more than one flip-flop.  In general, all async inputs are usually
first synchronized with the the internal clock before being used in a 
decision of the machine.

Dave Morano	AT&T	...!(ihnp4|houxm)!mtgzz!dam