Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!uwvax!oddjob!mimsy!umd5!brl-adm!adm!aglew%mycroft@gswd-vms.Gould.COM From: aglew%mycroft@gswd-vms.Gould.COM (Andy Glew) Newsgroups: comp.unix.wizards Subject: Re: Double-bit errors and ECC memory Message-ID: <9781@brl-adm.ARPA> Date: Thu, 15-Oct-87 05:50:25 EDT Article-I.D.: brl-adm.9781 Posted: Thu Oct 15 05:50:25 1987 Date-Received: Sat, 17-Oct-87 03:27:20 EDT Sender: news@brl-adm.ARPA Lines: 30 /* Written 11:08 pm Oct 14, 1987 by jerry@oliveb.uu in mycroft:fa.unix-wizards */ >Jerry Aguirre : >>Henry Spencer: >>Clearly, what we need, urgently, is ECC on the damn memory chips. There > >The disadvantage is that this provides less protection. Off chip ECC >protects against the total failure of the chip, not just the failure of >a bit or two. If an address or output line fails you would never know >about it with on-chip ECC. Maybe the place to put ECC is where the data is used - on the CPU chip, at the disk controller, and so on. This way you can detect and correct faults both at the memory chip, and in the interconnection. The trade-off is the number of wires in the interconnection, against the error rate due to the interconnection: wiring faults, EMI, etc. I suspect that the tradeoff lies with ECC on memory right now, but it may well move if interconnection costs fall (but error rates increase). Not also that interconnection complexity may decrease, if ECC is on chip at either end of the memory/cpu highway. Andy "Krazy" Glew. Gould CSD-Urbana. USEnet: ihnp4!uiucdcs!ccvaxa!aglew 1101 E. University, Urbana, IL 61801 ARPAnet: aglew@gswd-vms.arpa I always felt that disclaimers were silly and affected, but there are people who let themselves be affected by silly things, so: my opinions are my own, and not the opinions of my employer, or any other organisation with which I am affiliated. I indicate my employer only so that other people may account for any possible bias I may have towards my employer's products or it is as