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Path: utzoo!yetti!geac!daveb
From: daveb@geac.UUCP
Newsgroups: comp.arch
Subject: Re: Horizontal pipelining
Message-ID: <1782@geac.UUCP>
Date: Fri, 6-Nov-87 07:53:00 EST
Article-I.D.: geac.1782
Posted: Fri Nov  6 07:53:00 1987
Date-Received: Sun, 8-Nov-87 08:40:13 EST
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU> <2525@mmintl.UUCP>
Reply-To: daveb@geac.UUCP (Dave Collier-Brown)
Organization: The little blue rock next to that twinkly star.
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Keywords: multiple users

In article <2525@mmintl.UUCP> franka@mmintl.UUCP (Frank Adams) writes:
| I had an idea some time ago that I'm surprised I've never seen discussed.
| Suppose, for example, that your instruction processor has four stages.  With
| conventional pipelining, that means that four consecutive instructions from
| the same program are at some stage of execution at the same time.
| 
| Instead, why not have four different execution threads being performed
| simultaneously?

  A logically different but physically similar technique is used by
the Nippon Electric Company's DPS-90 series of processors: they keep
three pipelines around for pre-evaluating code down three possible
branches.  This cuts down on so-called "pipeline breaks" most
wonderfully in programs containing lots of branch instructions.
-- 
 David Collier-Brown.                 {mnetor|yetti|utgpu}!geac!daveb
 Geac Computers International Inc.,   |  Computer Science loses its
 350 Steelcase Road,Markham, Ontario, |  memory (if not its mind)
 CANADA, L3R 1B3 (416) 475-0525 x3279 |  every 6 months.