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Path: utzoo!yetti!geac!daveb
From: daveb@geac.UUCP
Newsgroups: comp.arch
Subject: Re: Horizontal pipelining
Message-ID: <1783@geac.UUCP>
Date: Fri, 6-Nov-87 07:56:34 EST
Article-I.D.: geac.1783
Posted: Fri Nov  6 07:56:34 1987
Date-Received: Sun, 8-Nov-87 08:41:22 EST
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU> <2525@mmintl.UUCP> <862@gumby.UUCP>
Reply-To: daveb@geac.UUCP (Dave Collier-Brown)
Organization: The little blue rock next to that twinkly star.
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Keywords: multiple users

In article <862@gumby.UUCP> earl@mips.UUCP (Earl Killian) writes:
>In article <2525@mmintl.UUCP>, franka@mmintl.UUCP (Frank Adams) writes:
>> Instead, why not have four different execution threads being performed
>> simultaneously?
>
>This is an old idea; it was done on the CDC 6600 i/o processors.  More
>recently it was tried on the HEP, which wasn't very successful.
> [explanation truncated]

  Many moons ago, ICL (the british mainframers) tried what my boss
called "half-caches", which as you might guess from the name,
allowed a cheap and easy swap from a running program to a
read-to-run program.  The system was really quite elegant (ie, it was
far easier than it looked), but I haven't heard anything on it since.
  Any ICLians out there?


-- 
 David Collier-Brown.                 {mnetor|yetti|utgpu}!geac!daveb
 Geac Computers International Inc.,   |  Computer Science loses its
 350 Steelcase Road,Markham, Ontario, |  memory (if not its mind)
 CANADA, L3R 1B3 (416) 475-0525 x3279 |  every 6 months.