Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!mit-eddie!uw-beaver!ubc-vision!alberta!edm!steve From: steve@edm.UUCP (Stephen Samuel) Newsgroups: comp.arch Subject: Re: H/W Write Buffers, S/W Synchronization Message-ID: <198@edm.UUCP> Date: Thu, 5-Nov-87 22:27:09 EST Article-I.D.: edm.198 Posted: Thu Nov 5 22:27:09 1987 Date-Received: Wed, 11-Nov-87 01:07:48 EST References: Organization: Unexsys Systems Inc., Edmonton,AB. Lines: 20 Summary: try forced sync writes. The only way I could see dealing with multiple processors and a write cache would be to have some method of forcing a write-thru. Some processors (like the 68000 series) have a signal to indicate a read/modify/write cycle. With processors like these, you would have to have your buffer respond to this signal by flushing the cache for that address -- both before the read and after the write. You have to flush before the read or else you can end up reading stale data on the cache. On systems without a locked-cycle signal, the only solution I can see is having some address to write to to signal that the next write (barring an interrupt is going to be a locked-cycle. In this case, the caches for ALL processors are going to have to respond to the signal or else you'll once again end up with the problem of stale read caches. -- ------------- Stephen Samuel Disclaimer: You betcha! {ihnp4,ubc-vision,seismo!mnetor,vax135}!alberta!edm!steve BITNET: USERZXCV@UQV-MTS