Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!utgpu!water!watmath!clyde!rutgers!rochester!cornell!batcomputer!pyramid!prls!mips!mash From: mash@mips.UUCP Newsgroups: comp.arch Subject: Re: RISC Message-ID: <901@winchester.UUCP> Date: Wed, 11-Nov-87 23:08:16 EST Article-I.D.: winchest.901 Posted: Wed Nov 11 23:08:16 1987 Date-Received: Sat, 14-Nov-87 12:52:59 EST References: <1656@geac.UUCP> <863@winchester.UUCP> <197@m2.mfci.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 34 Keywords: RISC,array In article <197@m2.mfci.UUCP> colwell@m6.UUCP (Robert Colwell) writes: >here...I see almost nothing RISCy about Pyramid or Ridge. Pyramid >seemed like a RISC to the novice because it had lots of registers >organized in windows, which was like RISC-I, and RISC-I is a RISC, >so Pyramid must be too? No way, unless you think the IBM 801 was >not. Pyramid RISCyness has been debated before in this newsgroup; personally, it seems like being on the CISCy edge of RISC to me, or RISCy edge of CISC, but it didn't seem reasonable not to mention it. Also, somebody from Celerity complained (probably fairly) on not being included in the list. What's un-RISCy about RIDGE? (allowing non-VLSI designs to be RISC) In any case, this wasn't supposed to be a definitive list, or detailed analysis, or any such thing, especially since we all know there's no such thing as a sharp boundary between RISC and CISC anyway. Certainly, the 801 is on the RISCy side of all this. >I notice that nobody has taken up Wirth's challenge at the ASPLOS-II... >integer overflows and broken floating point processing as being the >norm. I bet he knows this, but he didn't mention it. The >problem is that when you've got several streams of floating point >operations in the air at the same time, you could have a royal mess >if any one of them takes an exception AND you have to handle it a la >IEEE. One way out is to have the exceptions be flagged in a sticky >register, and check that register at the completion of the >computations; if clean, you win. Just out of curiosity, what DOES Multiflow do on this? One of your OS folks gave a good talk in my session at USENIX, but I don't recall how the IEEE-exception-handling was done. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086