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From: atbowler@orchid.UUCP
Newsgroups: comp.arch
Subject: Re: Horizontal pipelining
Message-ID: <11711@orchid.waterloo.edu>
Date: Fri, 13-Nov-87 18:42:36 EST
Article-I.D.: orchid.11711
Posted: Fri Nov 13 18:42:36 1987
Date-Received: Sun, 15-Nov-87 12:28:03 EST
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU> <2525@mmintl.UUCP> <1782@geac.UUCP>
Reply-To: atbowler@orchid.waterloo.edu (Alan T. Bowler [SDG])
Organization: U. of Waterloo, Ontario
Lines: 30
Keywords: multiple users

In article <1782@geac.UUCP> daveb@geac.UUCP (Dave Collier-Brown) writes:
>In article <2525@mmintl.UUCP> franka@mmintl.UUCP (Frank Adams) writes:
>| Instead, why not have four different execution threads being performed
>| simultaneously?
>
>  A logically different but physically similar technique is used by
>the Nippon Electric Company's DPS-90 series of processors: they keep
>three pipelines around for pre-evaluating code down three possible
>branches.  This cuts down on so-called "pipeline breaks" most
>wonderfully in programs containing lots of branch instructions.

It is amazing how people get excited ofer reinventing some really old
techniques.  "4 different execution threads" sounds like a conventional
multiprocessor system to me.  The GE-600 and its successors (including the
above mentioned DPS-90) have been doing this since the early sixties.
DPS-90 mentioned above) have done this since the early sixties.  The
multiple pipeline techinique within a single processor that Dave
describes is a somewhat newer technique (early seventies when I
heard IBM describe it for the 370/168) for getting faster performance
from a single instruction thread (processor).  Besides higher system
throughput, the multiprocessor approach increases reliability since
it is easy to get the system going again if one of the processors fails.
GCOS is perfectly happy to let a CPU be released serviced by the
field engineer, and returned to use with the user's never seeing
anything happen expect some responce time degradation.
DEC supported multiprocessors with the PDP-10 (a.k.a. system-20)
and Univac did it with the 1100 series.  IBM announced it several
times, but until the Sierra series never figured out how to make
the operating system handle it, so I suppose in the minds of many
people multiproccessors are brand new.