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From: ccplumb@watmath.waterloo.edu (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: Information Request: Sun's SPARC Chip
Message-ID: <15544@watmath.waterloo.edu>
Date: Fri, 13-Nov-87 20:38:28 EST
Article-I.D.: watmath.15544
Posted: Fri Nov 13 20:38:28 1987
Date-Received: Sun, 15-Nov-87 17:36:59 EST
References: <6310001@hpcupt1.HP.COM> <2411@im4u.UUCP> <18203@amdahl.amdahl.com>
Reply-To: ccplumb@watmath.waterloo.edu (Colin Plumb)
Organization: U of Waterloo, Ontario
Lines: 25
Confusion: U. of Waterloo, Ontario


chuck@amdahl.amdahl.com (Charles Simmons) writes:
>I've heard a rumor that the SPARC chip is implemented with rougly
>12,000 gates.  This seems pretty small, and definitely small enough
>to attract the attention of AT&T and Xerox.  With such a small number
>of gates, the SPARC chip should be implementable in ECL or GaAs, neh?
>Hasn't Sun farmed out production of the SPARC chip to some chip maker
>who will be building an ECL version of the chip?  Isn't the chip maker
>claiming they will get something like 20 or 40 VAX MIPS out of the chip?
>Wouldn't that excite AT&T and Xerox?

I heard 20,000, but either way, it is pretty small.  Fujitsu's current
implementation is a gate array, but Cypress (sp?) Semiconductor is
working on a 20 MHz custom CMOS version, and Bipolar Integrated
Technologies is working on a 100 MHz ECL SPARC.  How they'll get memory
that fast is beyond me, though I heard they were expecting only 50 MIPS
instead of the usual 1:1 MIPS:MHz ratio, which points to some wierdness.

As far as I know, no one's working on a GaAs version yet, even though
Sun talked up the idea.
--
	-Colin (watmath!ccplumb)

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