Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!amd!mikep From: mikep@amd.AMD.COM (mike parker) Newsgroups: comp.arch Subject: Re: Information Request: Sun's SPARC Chip Message-ID: <4670@amd.AMD.COM> Date: Sun, 15-Nov-87 12:56:48 EST Article-I.D.: amd.4670 Posted: Sun Nov 15 12:56:48 1987 Date-Received: Mon, 16-Nov-87 05:36:55 EST References: <6310001@hpcupt1.HP.COM> <2411@im4u.UUCP> <18203@amdahl.amdahl.com> <3084@psuvax1.psu.edu> <1889@ncr-sd.SanDiego.NCR.COM> Reply-To: mikep@amd.UUCP (mike parker) Organization: Advanced Micro Devices Lines: 43 Keywords: RISC, SPARC In article <1889@ncr-sd.SanDiego.NCR.COM> dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) writes: > >Fujitsu is implementing a gate array version of the SPARC. The part number >is MB86900. It runs at 16.67 MHz and is rated at 10 MIPS typ. > >Cypress Semiconductor is implementing a custom version of SPARC in .8 >Micron 2 layer Metal CMOS technology. The part number is CY7C601. It runs >at 25 MHz and is rated at 20 Equivalent VAX MIPS. > >BIT (Bipolar Integrated Technology) is implementing a full custom ECL >version of SPARC employing their BIT1 bipolar technology. >-- >Dennis Russell | NCR Corp., M/S 4720 Yes, this is the way I had heard it too, but it makes no sense. If they get 10 VAX MIPS at 16.67 then all other things being equal they need 33 MHz to get 20 VAX MIPS. The thing is that all other things are not equal, when you go twice as fast your memory system has to provide instructions twice as fast to maintain MIPS. Even worse, clock to Q on address lines and setup time on data lines don't necessarily get halved when clock rate doubles (because package capacitances don't change). This means that at twice the speed the memory chips have to be more than twice the speed of the ones used at the lower speed. If the memory performance doesn't keep up, then you get pushed from 0 wait states to 1 wait state and performance goes down. So SPARC won't do 20 VAX MIPS until they get to 33 MHZ chips and rams that are more than twice as fast as the ones they use now. Would somebody with a SUN 4 pop it open and tell me what speed SRAMS are used in the 128 Kbyte cache at 16.67 MHz? I am dying to know. mikep disclaimer: I have a vested interest as strategic marketing manager for the Am29000. I'm sure AMD doesn't accept responsibility for my opinions, especially on usenet. -- UUCP: {hplabs,amdcad,ihnp4,allegra}!amd!mikep ARPA: amdcad!amd!mikep@decwrl.dec.com USPS: Mike Parker, AMD, P.O. Box 3843, M.S. 6, Sunnyvale, Ca. 94088 AT&T: 408-982-6772