Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!mnetor!uunet!husc6!ut-sally!bcm!svedberg!rick From: rick@svedberg.bcm.tmc.edu (Richard H. Miller) Newsgroups: comp.arch Subject: Re: Horizontal pipelining Message-ID: <428@uni2.bcm.tmc.edu> Date: Sun, 15-Nov-87 17:11:19 EST Article-I.D.: uni2.428 Posted: Sun Nov 15 17:11:19 1987 Date-Received: Tue, 17-Nov-87 00:42:06 EST References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU> <11711@orchid.waterloo.edu> Sender: usenet@bcm.tmc.edu Lines: 50 Keywords: multiple users Summary: multiprocessing In article <11711@orchid.waterloo.edu>, atbowler@orchid.waterloo.edu (Alan T. Bowler [SDG]) writes: > Besides higher system throughput, the multiprocessor approach increases > reliability since it is easy to get the system going again if one of the > processors fails, GCOS is perfectly happy to let a CPU be released > serviced by the field engineer, and returned to use with the user's never > seeing anything happen expect some responce time degradation. > DEC supported multiprocessors with the PDP-10 (a.k.a. system-20) > and Univac did it with the 1100 series. IBM announced it several > times, but until the Sierra series never figured out how to make > the operating system handle it, so I suppose in the minds of many > people multiproccessors are brand new. Two points about the topics raised in the above. Unisys (a.k.a Sperry) still does it with the 1100 architecture. We can have up to four processors sharing common memory and executing common code. (Although an activity will only be running on one processor). If one processor fails, the system usually will be able to automatically down the failing instruction processor without the user being aware that there is a problem. This also extends to the mass storage (memory, not disk), IO processors, channels and controllers. In fact, under certain circumstances, different architectures can share common memory (the AVP on the 1100/70 allows a OS/3 system to run using the same memory as the 1100 and the ISP [Integrated Scientific Processor] allows a vector machine to run with the 1100/90 IP and Mass storage. Having been exposed to many types of architecture and machines, my view is that the 1100 line provides one of the nicest system environments for a large main frame system. (I do have a bias towards this system since it is our primary mainframe). The second point concerns the PDP-10. As I remember, TOPS-20 never was able to fully support Symmetric Multiprocessing but the TOPS-10 system did. Until the 7.01 release of TOPS-10, the PDP-10 systems used a master/slave relation- ship in multiprocessing. As of this release, the TOPS-10 was able to support true symmetric multiprocessing in that there was no master CPU. I/O could run from either CPU and it provided a true use of both processors. (Up until this release, the second processor usually was NOT as highly used as the master since I/O could only be handled by the master CPU and unless a shop was very CPU bound, it would not be able to utilize the second CPU fully.) The released product support up to 4 CPUs and several large TOPS-10 sites did run a quad system (altough it was never *officially* supported). Since we dropped out of the DEC world about 7 years ago, I never did hear if TOPS-20 ever got the capability. It is interesting that what I have read in the trades indicates that the VAX is to be given this capability that the TOPS-10 system had almost 7 years ago. Sigh Richard H. Miller Email: rick@svedburg.bcm.tmc.edu Head, System Support Voice: (713)799-4511 Baylor College of Medicine US Mail: One Baylor Plaza, 302H Houston, Texas 77030