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From: daveb@geac.UUCP
Newsgroups: comp.arch
Subject: Re: Horizontal pipelining
Message-ID: <1835@geac.UUCP>
Date: Mon, 16-Nov-87 09:11:26 EST
Article-I.D.: geac.1835
Posted: Mon Nov 16 09:11:26 1987
Date-Received: Tue, 17-Nov-87 04:08:23 EST
References: <201@PT.CS.CMU.EDU> <8801@utzoo.UUCP> <8758@shemp.UCLA.EDU> <2525@mmintl.UUCP> <1782@geac.UUCP> <11711@orchid.waterloo.edu>
Reply-To: daveb@geac.UUCP (Dave Collier-Brown)
Organization: The little blue rock next to that twinkly star.
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Keywords: multiple users

In article <11711@orchid.waterloo.edu> atbowler@orchid.waterloo.edu (Alan T. Bowler [SDG]) writes:
> ... The
>multiple pipeline technique within a single processor that Dave
>describes is a somewhat newer technique (early seventies when I
>heard IBM describe it for the 370/168) for getting faster performance
>from a single instruction thread (processor).

Hi, Alan!

  I confess I don't remember IBM actually *having* the multiple
pipelines in the /168... although I do remember it being proposed
when UofWindsor still had one.
  Did they get it shoehorned in?

 --dave (formerly brown) c-b
-- 
 David Collier-Brown.                 {mnetor|yetti|utgpu}!geac!daveb
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