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From: raj@hubcap.UUCP (R Parthasarathy)
Newsgroups: comp.arch
Subject: Chip Area Distribution in processors
Message-ID: <677@hubcap.UUCP>
Date: Tue, 17-Nov-87 23:07:40 EST
Article-I.D.: hubcap.677
Posted: Tue Nov 17 23:07:40 1987
Date-Received: Sat, 21-Nov-87 00:35:53 EST
Organization: Clemson University, Clemson, SC
Lines: 26
Keywords: VLSI Design, Layout, Design Trade-offs


    I've been investigating an issue regarding chip area distribution for processors.  Computer Architects (those who are not particularly proficient in VLSI design and Layout) need a reasonable understanding of how much chip area is taken
up by the different resources on a chip in order to make design decisions. 
    Particularly, it is required to have a clear understanding of how much space
is saved by giving up a certain feature, so that something else may be included
instead. Normally, this kind of information is with persons having industrial
design experience and not with those dabbling in theoritical computer 
architecture. Questions are ....

1. Are there any existing models which quantify the allocation of chip  area       for the various resources?
2. If so, then are these models very much technology dependent (i.e. Nmos,Cmos
   .... etc.)?
3. Any references?

   I would like to listen to the opinions of this newsgroup readers. Any takers?
Thanks in advance.

-------------------------------------------------------------------------------
Rajan Parthasarathy                 email:- {ihnp4,hao}!gatech!hubcap!raj
Box 5802, Univ Station                            raj@hubcap.clemson.edu
Clemson, SC 29632                   Disclaimer:- I speak for myself.
Ph-(803)-654-3705