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From: raj@hubcap.UUCP (Rajan Parthasarathy)
Newsgroups: comp.arch
Subject: Chip Area Distribution in Processors
Message-ID: <679@hubcap.UUCP>
Date: Wed, 18-Nov-87 00:17:23 EST
Article-I.D.: hubcap.679
Posted: Wed Nov 18 00:17:23 1987
Date-Received: Sat, 21-Nov-87 00:37:02 EST
Organization: Clemson University, Clemson, SC
Lines: 25
Keywords: VLSI Design, Layout, Design Trade-offs


I've been investigating an issue regarding the chip area distribution for
processors. Computer Architects (those not particularly proficient in VLSI
design and layout) need to have a reasonable understanding of how much chip
area is taken up by the different resources, in order to make design decisions.

Particularly, it is required to know how much chip area is saved by giving up
a certain feature in the architecture, so that something else may be included.
Normally, this kind of information is with persons having years of design 
experience in the industry and not with those dabbling in thoretical computer
architecture (please, no flames if I have offended anyone). Questions are.....

1. Are there any existing models which quantify the allocation of chip area 
   between resources?
2. If so, then, are these models very much technology dependent (i.e. NMOS,
   CMOS.. etc.)?
3. Any references?

  I would like to listen to the opinions of this newsgroup readers. Any takers??

------------------------------------------------------------------------------
Rajan Parthasarthy                        email:-{ihnp4,hao}gatech!hubcap!raj  
Box 5802, Univ Station                                 raj@hubcap.clemson.edu
Clemson, SC 29632                      General Disclaimer:I speak for myself.
Ph-(803)-654-3705