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From: raj@hubcap.UUCP (Rajan Parthasarathy)
Newsgroups: comp.arch
Subject: Chip Area Distribution in processors
Message-ID: <685@hubcap.UUCP>
Date: Wed, 18-Nov-87 13:50:51 EST
Article-I.D.: hubcap.685
Posted: Wed Nov 18 13:50:51 1987
Date-Received: Sat, 21-Nov-87 10:10:39 EST
Organization: Clemson University, Clemson, SC
Lines: 24
Keywords: VLSI design, Layout, Design Trade-offs


  I've been investigating an issue regarding chip area distribution for
current micro-processors. Computer Architects (those who are not particularly
proficient in VLSI design and layout) need to have a clear understanding of
how the area is allocated to different resources on a chip.
  Particularly, it is required to know how much of the area can be saved by
giving up a certain feature in the design, so that something else may be 
included. Normally, this info is with persons having years of design experience
in the industry and not with those dabbling in theoritical computer architecture (please, no flames if I have offended anybody). Questions are....

1. Are there any existing models which quantify the allocation of chip area for 
   the different resources on a chip ?
2. If so, are these models very much technology dependent (i.e.NMOS,CMOS etc.) ?
3. Any references ?

  I would like to listen to the opinions of this newsgroup readers. Any takers..
Thanks in advance

--------------------------------------------------------------------------------

Rajan Parthasarathy                       email:- ....gatech!hubcap!raj
Box 5802 Univ Station               on internet:-     raj@hubcap.clemson.edu 
Clemson,  SC 29632                   General Disclaimer:- I speak for myself.
Ph-(803)-654-3705