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From: rbl@nitrex.UUCP ( Dr. Robin Lake )
Newsgroups: comp.arch
Subject: Re: Information Request: Sun's SPARC Chip
Message-ID: <578@nitrex.UUCP>
Date: Fri, 20-Nov-87 09:01:34 EST
Article-I.D.: nitrex.578
Posted: Fri Nov 20 09:01:34 1987
Date-Received: Mon, 23-Nov-87 05:53:57 EST
References: <6310001@hpcupt1.HP.COM> <2411@im4u.UUCP> <18203@amdahl.amdahl.com> <3084@psuvax1.psu.edu> <1889@ncr-sd.SanDiego.NCR.COM>
Reply-To: rbl@nitrex.UUCP ( Dr. Robin Lake )
Organization: The Standard Oil Co., Cleveland
Lines: 19

In article <1889@ncr-sd.SanDiego.NCR.COM> dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) writes:
>In article <18203@amdahl.amdahl.com> chuck@amdahl.amdahl.com (Charles Simmons) writes:
>>> With such a small number
>>>of gates, the SPARC chip should be implementable in ECL or GaAs, neh?
>>>Hasn't Sun farmed out production of the SPARC chip to some chip maker
>>>who will be building an ECL version of the chip? 
>>
>
>Fujitsu is implementing a gate array version of the SPARC.  The part number
>is MB86900.  It runs at 16.67 MHz and is rated at 10 MIPS typ.

Does the SPARC design support cache coordination so that parallel processing
is easily supported?

Rob Lake
BP America R&D
-- 
Rob Lake
{decvax,ihnp4!cbosgd}!mandrill!nitrex!rbl