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From: sgcpal@watdcsu.UUCP
Newsgroups: comp.lsi
Subject: Re: SPICE 2g6
Message-ID: <4084@watdcsu.waterloo.edu>
Date: Fri, 6-Nov-87 11:35:27 EST
Article-I.D.: watdcsu.4084
Posted: Fri Nov  6 11:35:27 1987
Date-Received: Sun, 8-Nov-87 10:15:14 EST
References: <3986@venera.isi.edu> <8711050122.AA14933@vlsi.cs.washington.edu>
Reply-To: playman@phonon.waterloo.edu (P.A.ul Layman [EE-Device Physics])
Distribution: world
Organization: U. of Waterloo, Ontario
Lines: 59


In article <8711050122.AA14933@vlsi.cs.washington.edu> larry@VLSI.CS.WASHINGTON.EDU (Larry McMurchie) writes:
>
>
>The recent note that appeared describing a difference between the
>version of SPICE 2g6 distributed by Berkeley and the version
>distributed by us is indeed correct.
>
>On line 1985 of file dctran2.f, the last variable used to calculate
>FACTOR should be XL (not XW). The line should read:
>
>  200 FACTOR=0.125D0*FNARRW*TWOPI*EPSSIL/COX*XL
>
>What can I say....we goofed.  

Maybe you didn't.  At least not totally anyway.

We noticed this difference when we ran diff on the two
distributions and I'm afraid both versions maybe wrong.

Here is the original ucb version:
C
C  CALCULATE THRESHOLD VOLTAGE (VON)
C     NARROW-CHANNEL EFFECT
C
  200 FACTOR=0.125D0*FNARRW*TWOPI*EPSSIL/COX*XL
      ETA=1.0D0+FACTOR

I think line 200 should be:

  200 FACTOR=0.125D0*FNARRW*TWOPI*EPSSIL/(COX*XW)

Note the change from XL to XW and the inclusion of the brackets
around the (COX*XW).

Intuitively one would think that the width (XW) would be a factor
in the narrow width calculation.

This change is required to conform with the spice mos2 model
documents (ERL memo) giving:

	eta = 1 + fnarrw pi epsilon(silicon)
			 ___________________
			 4 Cox W

and to ensure that eta is dimensionless rather than something strange
(1 + m**2).

It would appear to me that the original UW distribution tryed to
rectify the UCB error, but only went half way.  Am I right, or am
I missing something?

Paul A. Layman

University of Waterloo, Electrical Engineering,
Silicon Devices and Integrated Circuits Research Group (SiDIC)

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