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From: kamath@reed.UUCP (Sean Kamath)
Newsgroups: comp.sys.apple
Subject: ZIP chip (and my AppleFest tome)
Message-ID: <7640@reed.UUCP>
Date: Thu, 5-Nov-87 00:35:49 EST
Article-I.D.: reed.7640
Posted: Thu Nov  5 00:35:49 1987
Date-Received: Sun, 8-Nov-87 07:00:51 EST
Reply-To: kamath@reed.UUCP (Sean Kamath)
Organization: Reed College, Portland OR
Lines: 36


I am about to post my AppleFest tome, in two parts, but here is a quick
rundown on the zip chip.  

It is almost exactly like the speed demon.  This is because it was
designed by the same people.

The chip has onchip caching, which is better than a ton-o-fast RAM (I
feel) because it's cheaper.  I cannot remember exactly how much it
cache's but it's enough.  They experimented with different sizes, and
the performance increase with (how much?  64K or something huge) was
only 10-20% and really not worth the price at all.

It is a 4 MHz 65C02 with an internal clock and it's asunchronous, so it
works in a ][+ as well as a //e (they say).  You can devide the clock to
anything you want (I assume a 2 byte devisor, thus 65535 different
speeds, but most people will use faast or slow. . .).

The chip is programmable, comes with a disk that configures it, startup
programs for DOS 3.3 as well as ProDos that sets the chip automatically
to a preset configuration, and two memory and MMU test programs.  It
also has the instructions on disk.

The chip can be configured much the same as most cards, with additions.


For a more detailed discription, read my mondo big opinion sheet. . .
Coming NEXT!!!!!!! (next from me, that is!  It's DONE!)

Sean kamath

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