Path: utzoo!mnetor!uunet!husc6!mit-eddie!uw-beaver!cornell!batcomputer!itsgw!steinmetz!sunray!oconnor From: oconnor@sunray.steinmetz (Dennis M. O'Connor) Newsgroups: comp.arch Subject: Re: Impossible 40MHz R2000 ?? Message-ID: <8252@steinmetz.steinmetz.UUCP> Date: 17 Dec 87 22:30:55 GMT Sender: root@steinmetz.steinmetz.UUCP Reply-To: sunray!oconnor@steinmetz.UUCP Organization: GE Corporate R&D Center Lines: 163 Keywords: fast faster fastest micro east of the GaAs :-) Summary: How about "Impossible 40MIPS R2000" (i.e. 80MHz) An article by hansen@mips.UUCP (Craig Hansen) says -] Quoting jesup@pawl22.pawl.rpi.edu (Randell E. Jesup) : -]] The real problem is the fact that your chip edge is clocked at twice your -]] instruction freqency. Running a higher-speed clock than the instruction -]] rate is fine, and makes internal design much easier. However, packaging -]] technology will be your limiting factor for some time to come, not really -]] ram speed per se. For the large number of pins required, it is hard to -]] find packages certified at that speed. -] -]For speeds well above 40 MHz in CMOS technology, our studies suggest that this -]will not be a limiting factor at all ... You missed the point. The relevent number isn't 40MHz, it's 40MIPS. To achieve that, you'll need 80 MHz. Mr. Jesup ( hi Randell ) has personal knowledge of a 40MHz 40MIPS CMOS microprocessor, as do I, that is real silicon, really working, right now. Those are of course raw machine MIPS, not equivalent anything MIPS. Check out the upcoming ISSCC conference for more details. -] ... But the other companies chip had double-frequency clock inputs, -] too, and when you compared the two chips at their specified clock -]rate, ours runs more than twice as fast (benchmark-wise), and theirs had double -]the input clock rate. Talk about double-speak! The chip Randal and I know of uses a two-phase 40MHz clock two achieve 40 MIPS. The smallest important time interval is 2ns. You'll need, I think, a four-phase 80MHz clock for 40 MIPS. I don't know what the smallest important time interval will be for your clocks. -] [ ... a bunch of non-sequitors deleted ... ] -] Because SRAMs are used as technology drivers for new CMOS and BiCMOS -] technologies, MIPS can be assured of a good supply of highly -] agressive SRAMs that will work with the MIPS part. Actually, GE's 1.25 micron AVLSI CMOS process is one of the best going (ask IBM about it) and never had anything to do with RAMs. Oh since you brought it up, the machine Randal and I know of uses 20ns CMOS RAMs to run at 40MIPS with no wait states. What will you need? -]The real problem with the other RISC designs ... -] [massive generalization deleted] What limited-omniscience you must have, to be able to tell all of us the ONE TRUE PROBLEM with "other" RISC designs. :-) Baloney. What do you know about MY RISC machine? Nothing. So pay attention at ISSCC and learn a few things. ALSO, An article by mark@mips.UUCP (Mark G. Johnson) says: -] Quoting from author jesup@pawl22.pawl.rpi.edu (Randell E. Jesup) -]] Given current technology, r2000 could probably be scaled -]] to about 20 MHz. However, custom RISC designs in CMOS are -]] now reaching 40 MHz, which would be impossible with the -]] double-clocked interface currently on the r2000. Perhaps -]] the interface could be removed, given enough pins, but -]] that gets you back into the packaging limits. -] -]"Impossible" is quite a strong word. "Difficult", sure. But he's -]saying that a 2.4X improvement of a first-chip-designed-at-a-startup- -]company, 2-micron-generic-silicon-foundry device is IMPOSSIBLE. -] -]A few things might change :-) :-) between now (16.7 MHz) and 40 MHz. No No NO, 40 _MIPS_, not MHz. 80MHz for you guys. And since it is already here, your changes better happen yesterday. Randel, you shoulda said 40MIPS, you know how easily confused people get :-) -] [ ... standard "learn from experience" stuff deleted ... ] -] -]Other factors conspire to make the job of building a 40 MHz -]double-clocked interface not "impossible": -] -] 1. Cache RAM access times will continue to decrease, likely -] at the same rate as the processor clock, since SRAM vendors -] now build RISC chips (including SPARC, R2000, Am29K). So -] RAM access time will probably stay at 40-50% of processor -] cycle time. {presently 60 ns cycle, 25-30 ns RAM access}. Anyone who thinks system access time for a given memory system architecture will decrease linearly with RAM access into the tens-of- nanoseconds range is dreaming. Go figure your peak amps per volt of swing when trying to charge 120pf in 3 nanoseconds. Run that through your bonding wires and smoke it :-). Also the idea that there is a linear relationship between how fast a particular fab technology can make RAMs and how fast the technology can make CPUs ignores a lot of important differences between the two. For instance, how much difference do you think having two levels of metal makes to a RAM, and how much to a CPU ? Think about it. -] 2. Surface mount packages (having [...] leads, 144) might be -] used instead of the [... PGA]. ... lower inductance ... -] controlled impedance ... improve signal quality ... -] more than 2.4X better than the existing PGA package ... -] "timing slop" would decrease. Package isn't that important. The dielectric constant of your substrate and the size of your input protection are probably going to limit you first. Besides, surface-mounts beyond 132 or so have a tendency to jump off the board when thermal-cycled. No fun. -] -] 3. Output voltage drive levels might shrink ... to (an -] example) 0.4V and 2.7V. ...speeds up output transitions... -] without increasing switching noise. Less of the cycle (in -] percentage terms) would be spent slewing the bus around. Yes, this is true. But the processor Randal and I know of ( but aren't really allowed to say much about ) uses good old 5V swings, like the fast CMOS RAMs it's hooked to and the Sun that drives talks to it :-) If IT goes to 3V, well, we'll have to see. Don't have crystal ball. Also, what abouth second order effects in the MOS transistors, and what about noise rejection ? Its just not as simple as lowering the supply. -] 4. The clock generation and distribution technology may -] get a factor of -] 2.4X more precise ... -] "slop" (timing edge uncertainty) would go down. "You cannae change the laws of physics, laws of physics, laws of physics, You cannae change the laws of physics, laws of physics, Captain !" from _Star Trekkin'_, by The Firm. " Our new supraluminal wave guide... " "Don't put your finger near the board, the stray capacitance will kill the clock system..." Look, using transmission lines instead of wires is one way to go and yes it would help. But until then your just doing that old RC game. In the imperfect noisy nonlinear real world. Sigh. -] 5. BiCMOS fab processes might be employed, permitting the -] use of open emitter, Wired-OR interfacing to ECL-compatible -] cache RAM chips. Current ECL RAMs are about 15-20 nsec, -] a smaller fraction of the current processor cycle (60 nsec) -] than current MOS RAM chips. So the timing margins -] *improve*. Additionally, multiple-driver "collisions" or -] "contention" are non-deadly in the wired-OR ECL structure, -] (unlike CMOS tristate busses), such that the time between -] disabling X and enabling Y onto the bus, can be reduced -] dramatically. And there's reason to believe that BiCMOS -] RAM access times will scale at about the same rate as -] traditional CMOS RAMs. Sure, but when YOU use 20ns RAM you get what, 20MIPS? And when I use 20ns RAM I get (am getting) 40MIPS. So who is better positioned to take advantage of new RAM technology? -]Taken individually or as a group, these scenarios indicate (at least -]to me) that 40 MHz "double clocked cache interfaces" are indeed -]possible, and might in fact be as robust (or moreso) than existing -]implementations at 16.7 MHz. -] -]Regards, -] -]-Mark Johnson *** DISCLAIMER: The opinions above are personal. *** Sure, and warp drive may be safer than skiing. Cutting edge NOW is 40MIPS at 40MHz-2-phase using 20ns RAMs. The future may belong to GaAs. Are you in the present or the past ? Gee, I wish I could tell you more about our chip. Maybe after ISSCC I'll be able to. Like, knock off your socks, fur sure. -- Dennis O'Connor oconnor@sungoddess.steinmetz.UUCP ?? ARPA: OCONNORDM@ge-crd.arpa "If I have an "s" in my name, am I a PHIL-OSS-IF-FER?"