Path: utzoo!mnetor!uunet!husc6!hao!ames!sdcsvax!ucsdhub!hp-sdd!hplabs!hpda!hpcupt1!fotland
From: fotland@hpcupt1.HP.COM (Dave Fotland)
Newsgroups: comp.arch
Subject: Re: Brain-Clogging Decimal (Was: Re: Wirth's challenge (Was Re: RISC))
Message-ID: <6310002@hpcupt1.HP.COM>
Date: 24 Dec 87 04:06:19 GMT
References: <15782@watmath.waterloo.edu>
Organization: Hewlett Packard, Cupertino
Lines: 47

>For symbolic languages, tagged pointer
>operations are very important.  Typically, tagged dispatch and tagged
>pointer following are done quite a lot, and cutting the number of
>machine instructions to do these things can make quite a difference in
>performance.  Take the example of following a tagged pointer.  If
>the tag is kept in the high few bits of a 32 bit address, one must and the
>pointer with a 32 bit constant.  Quite a lot of overhead, when a simple
>addressing mode that ignored the high, say, 4 bits of the address would
>do the trick perfectly.  I know this runs contrary to the RISC ideal.
>But on a CISC, this is no more arcane than some of the other addressing
>modes.  

On the HP precision architecture, loads are indexed with index
shifting according to the operand size.  If the upper two bits are the 
tag, and the pointer is 32 bits, the load word will shift the index left 
two bits, and ignore the tag.  No requirement for anding registers and no
extra instructions on this RISC machine!  If a bigger tag is needed,
we only need one extra instruction, an extract, which can be used to
strip off the tag.

>Similarly for tagged dispatch.  If there were an instruction to take
>the top, say, 2 bits of a register, shift them right a whole bunch of
>places, add them to a given address, and jump to the address stored
>there.  Sure, this could be done with a shift or rotate, an and, an add,
>and an indirect jump.  But wouldn't you rather do one instruction than
>4?

In HP precision architecture there are exactly the primitives you
want, the extract instruction, which extracts a bit field from
a word and right justifies it in the result.  We paid a lot of
attention to instruction count when we were designing HP-PA, and
we found that operating systems and LISP did a lot of bit field
manipulation so we included extract and it's converse, deposit,
in the instruction set.  Your tagged dispatch would be an extract
followed by a load and a branch.  Three instructions, but just as
fast as the microcoded single instruction on the CISC machine.

>The point machine designers should take into account is that more and
>more, people are buying general-purpose hardware rather than the
>expensive specialized hardware.  Therefore, they should design their
>machines taking symbolic languages, CAD, and other specialized tasks
>into account.

I agree!  But general purpose does not have to mean CISC!  HP-PA is
a general purpose RISC architecture.

-David Fotland fotland@hpda.HP.COM