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From: cik@l.cc.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: Gate counts for implementations of architectures
Message-ID: <640@l.cc.purdue.edu>
Date: 1 Jan 88 11:40:23 GMT
References: <3793@ames.arpa>
Organization: Purdue University Statistics Department
Lines: 29
Keywords: RISC, gates, instruction set

In article <3793@ames.arpa>, lamaster@ames.arpa (Hugh LaMaster) writes:
 
> Is it worth it to add a particular function?  
> 
> For example, various Cray CPU's have had about 500K gates in them: this
> includes hardware integer add, multiply, divide, floating add, multiply,
> reciprocal approximation (fully segmented), and shift/mask instructions.
> The Cyber 205 has about twice as many gates - and has a 
> slower clock speed.  Are the extra gates worth it on the Cyber 205, even
> at the cost of having a slower clock speed (note: it is easy to find
> applications which make either machine look faster)?  ........

It is not obvious that the difference in speeds is due to the number of gates.
There are many situations in which the 205 is much faster.  Multiple precision
arithmetic is not a piece of cake on the 205, although double precision
(actually 1.95 precision) is not difficult.  Even getting the least sugnificant
part of a product of single precision numbers is a beast on the Cray.  If a
function needs different algorithms for different parts of its domain, the
separation and subsequent merging on the 205 is trivial; on the Cray it is
difficult.  The paucity of computational registers on the Cray can cause an
inordinate time to be spent on loads and stores, although these are much faster
on the Cray.  Each vector pipeline on the 205 has its set of gates; the Cray
does not have vector pipelines, but requires that the vectors for computation
be in registers.  (As you may gather from my comments, I believe not only in
CISC, but in VCISC.)
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (ARPA or UUCP) or hrubin@purccvm.bitnet