Path: utzoo!utgpu!water!watmath!clyde!rutgers!lll-lcc!pyramid!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: comp.arch Subject: Re: a thought provoking note on RISC processors Keywords: humerous contradictory Message-ID: <1253@winchester.UUCP> Date: 8 Jan 88 09:27:09 GMT References: <1007@pembina.UUCP> <490@auvax.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 26 In article <490@auvax.UUCP> rwa@auvax.UUCP (Ross Alexander) writes: >In article <1007@pembina.UUCP>, steve@alberta.UUCP (Steve Sutphen) writes: >Perhpas he meant `compatible with ns32K-series mmu, fpu, and/or peripheral >chips'; that is, buss compatible with the ns32k? This is at least plausible, especially for the peripheral chips. In any case, it would seem unlikely (and probably unwise) for NSC to be pouring resources into a RISC chip design at this point. Only the first few entrants into a market have much chance, and if you didn't start 2-3 years ago, it's too late for this one. Observe that the most aggressive "early adopters" either built their own RISC architecture before 1986, or if not building their own, selected one and got going with it either in 1986 or 1987. Almost anybody else in the computer business, if they go RISC at all, and if not doing their own, will pick sides during 1988 and get designs going. Common wisdom says that if you can't be 1st, 2nd, or (maybe) 3rd in a market, you ought to stay out of it, unless you can segment it somehow to get a bigger share. Hence, one would expect that it would be sane for NSC to stay away from this one and concentrate on places where the 532 can win. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086