Path: utzoo!mnetor!uunet!husc6!cmcl2!brl-adm!brl-smoke!gwyn
From: gwyn@brl-smoke.ARPA (Doug Gwyn )
Newsgroups: comp.sys.apple
Subject: Re: Synchronous (HDLC) GS?
Message-ID: <6891@brl-smoke.ARPA>
Date: 20 Dec 87 01:41:26 GMT
References: <8712181616.AA20668@mitre.arpa>
Reply-To: gwyn@brl.arpa (Doug Gwyn (VLD/VMB) <gwyn>)
Organization: Ballistic Research Lab (BRL), APG, MD.
Lines: 13

In article <8712181616.AA20668@mitre.arpa> mcgurrin@MITRE.ARPA writes:
>In browsing through the IIGS hardware and firmware technical manuals, I noticed
>that the serial port uses a multi-protocol chip that supports synchronous
>as well as asynchronous communications.

I seem to recall from looking through the schematics that the chip was
hard-wired into the machine in a way that assumed it would be used in
serial mode only.  However, I might be mistaken.  You can certainly
directly access the chip registers to request HDLC etc. modes; several
months ago I posted a C header file containing appropriate definitions.
If you need a copy, send me mail with a return address that I can parse
(none of this BITnet nonsense!)
	-- Gwyn@BRL.MIL