Path: utzoo!utgpu!water!watmath!clyde!rutgers!ames!pasteur!ucbvax!hplabs!hpcea!hpnmd!hpsrla!brucek
From: brucek@hpsrla.HP.COM (Bruce Kleinman)
Newsgroups: comp.arch
Subject: Re: 68020 - Indirect Post-indexed
Message-ID: <3460010@hpsrla.HP.COM>
Date: 14 Jan 88 23:11:24 GMT
References: <93900009@hcx2>
Organization: HP Network Measurements Div - Santa Rosa, CA
Lines: 18

+-------
| Don't ask me how many cycles these stupid addressing modes take, I get
| nauseous at the thought.  Good luck 68040.
+-------
I don't know about the 68040, but I have some numbers for the '030.  Quoting
from the depths of the 68030 User's Manual, section 11.6.1, the Fetch 
Effective Address Table.  This table "indicates the number of clock periods
needed for the processor to caclulate and fetch the specified effective
address."  Hence, instruction execution is not included.

        I-Cache Case      12 cycles
        No-Cache Case     14 cycles

Now if they can only design a 16-stage pipeline for the 68040, we'll have
single cycle execution AND backward compatibilty :-)


Bruce Kleinman  ( brucek%hpnmd@hplabs.hp.com )