Path: utzoo!utgpu!water!watmath!clyde!rutgers!cmcl2!nrl-cmf!ames!sdcsvax!ucsdhub!hp-sdd!hplabs!decwrl!sun!pitstop!sundc!seismo!uunet!steinmetz!sunray!oconnor
From: oconnor@sunray.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion
Keywords: bandwidth datapath 128
Message-ID: <8843@steinmetz.steinmetz.UUCP>
Date: 15 Jan 88 17:18:01 GMT
Sender: news@steinmetz.steinmetz.UUCP
Reply-To: sunray!oconnor@steinmetz.UUCP
Organization: GE Corporate R&D Center
Lines: 50

An article by physh@unicom.UUCP says:
 [ proposes increasing computer performance by making busses
   128 bits wide, while leaving data-paths 32-bits wide ]

Comments :
1. We're not talking a microcomputer here, not with current
   packaging & interconnect technology. So for now this
   proposal is only applicable to super-minis, mainframes
   and super- or hyper-computers.

   ( A hyper-computer is a super-computer being promoted
     by an over-excited marketing division :-)

   Many machines do what you have proposed, on the "far" (non-CPU)
   side of their caches. Even micros can do this, since cache
   data width isn't as limited by pins-per-package as CPU
   bus width is in a microcomputer.

2. When considering the total system cost of such a machine,
   the CPU datapaths are only a small part. Admittidly making
   them 64 bits wide may slow them down ( adds 1 gate delay
   to your carry chain, plus higher parasitics and greater
   distance between components ) but for many applications
   ( like banking, where you need to keep track of more than
   16 billion tenths-of-a-cent ( $160 million ), and scientific
   computing, where double-precision is becoming the LEAST
   precise thing people are willing to use ) you probably win.

3. When you mentioned fetching instructions, you seemed to assume
   that instruction size had to equal data word size. This isn't true.
   There is no direct relation between word size and instruction
   size. There is some relation between word size and address space
   ( if you have n-bit data paths, you ought to have n-bit addresses,
    and vice-versa. This is just a sensible opinion ? )

To sum it all up : Yes the idea is good, it is used already,
and yeilds higher memory bandwidth at reduced cast. But it's not
practical for single-chip implementation yet : when we get
beyond 244-pin high-speed packages ( e.g. wafer-scale, or
whatever other high-density interconnect technology you like )
then it will probably be used in the micro arena.

This feature migration from mainframes to micros is not
at all uncommon. Or unexpected.


--
	Dennis O'Connor 	oconnor@sungoddess.steinmetz.UUCP ??
				ARPA: OCONNORDM@ge-crd.arpa
        "If I have an "s" in my name, am I a PHIL-OSS-IF-FER?"