Path: utzoo!utgpu!tmsoft!mason
From: mason@tmsoft.UUCP (Dave Mason)
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion (really sequent cache)
Message-ID: <262@tmsoft.UUCP>
Date: 16 Jan 88 18:55:48 GMT
References: <235@unicom.UUCP> <8844@steinmetz.steinmetz.UUCP>
Reply-To: mason@tmsoft.UUCP (Dave Mason)
Followup-To: comp.arch
Organization: TM Software Associates, Toronto
Lines: 22

In article <8844@steinmetz.steinmetz.UUCP> davidsen@crdos1.UUCP (bill davidsen) writes:
>Sequent reduces bus usage by having a local cache and delayed write
>through. When a value is modified in the cache, it is *not* written to
>memory. Only when the value is flushed from cache, or when another
>processor reads the value, is the modified value placed on the bus. When
>another processor reads the value, the processor cache which contains
>the most recently modified version of the data places it on the bus, and
>the other processor *and the memory* are updated.

There's actually a bit more to it than this.  A processor only changes
the cache if it has EXCLUSIVE ownership of the word (in fact every
write to memory is treated this way, I believe).  When another
processor asks for a word, the owner gives it (rather than memory),
but also holds on to it, marking it as shared ownership (the requestor
also marks it as shared ownership).  Then before modifying it, a
processor negociates over the bus for exclusive ownership.  Many
processors may simultaneously hold a word for shared access.

  I think this is a particularly elegant solution to the cache
coherency problem.  Does anyone know if Sequent invented it (seems
rather too obvious for that), or a proper reference to who did? 
	../Dave