Path: utzoo!utgpu!water!watmath!clyde!rutgers!cmcl2!nrl-cmf!ames!pasteur!ucbvax!hplabs!pyramid!prls!mips!mash
From: mash@mips.UUCP (John Mashey)
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion
Keywords: bandwidth datapath 128
Message-ID: <1347@winchester.UUCP>
Date: 17 Jan 88 21:24:32 GMT
References: <8843@steinmetz.steinmetz.UUCP> <221@imagine.PAWL.RPI.EDU>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 14

In article <221@imagine.PAWL.RPI.EDU> userfe0e@mts.rpi.edu (George Kyriazis) writes:
.....
>but for only one instruction.  Can a compiler succesfully put 3 useful
>instructions after the jump?? ....
No:
	1st delay slot: fill 70+% of the time, or more
	2nd: a lot less (studied at Stanford; I don're recall the results,
		because they were low enough we never considered it)
	3rd: forget it.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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