Path: utzoo!mnetor!uunet!portal!cup.portal.com!Steve_D_Wilson
From: Steve_D_Wilson@cup.portal.com
Newsgroups: comp.arch
Subject: Re: Impossible 40MHz R2000 ??
Message-ID: <2367@cup.portal.com>
Date: 10 Jan 88 17:54:33 GMT
References: <1145@mips.UUCP>
Organization: The Portal System (TM)
Lines: 13
XPortal-User-Id: 1.1001.1957


Just a quick comment on your statements concerning ECL.  There
are two points that should be made.

1) Current ECL rams aren't at 15-20 ns as stated, there down
   at 7 to 8 ns and with the advent of self-timed write
   curcuitry, will approach 3 to 5 ns cycle times.

2)  When you WIRE-OR ECL drivers you pay a price in performance.
    There is a timing penalty that must be payed when you have
    more than one driver on the line, and it isn't small.  At
    the last company I worked at the expected hit for using a
    WIRE-OR was greater than 2 ns WITHOUT adding in the delay
    due to driver separation reflections and such.