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From: jesup@pawl19.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: Impossible 40MHz R2000 ??
Message-ID: <207@imagine.PAWL.RPI.EDU>
Date: 12 Jan 88 05:25:49 GMT
References: <1145@mips.UUCP> <2367@cup.portal.com>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: beowulf!lunge!jesup@steinmetz.UUCP
Organization: RPI Public Access Workstation Lab - Troy, NY
Lines: 16

In article <2367@cup.portal.com> Steve_D_Wilson@cup.portal.com writes:
>1) Current ECL rams aren't at 15-20 ns as stated, there down
>   at 7 to 8 ns and with the advent of self-timed write
>   curcuitry, will approach 3 to 5 ns cycle times.

	Sorry if you misunderstood, 15-20ns was for static CMOS rams, not
for ECL.

	I hope they can get that fast, as we will see GAAS chips of >100 MHz,
maybe even 200 MHz, eventually.  Of course, they have to get gaas to yield
with lots of gates, first.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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