Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!necntc!ima!johnl
From: johnl@ima.ISC.COM (John R. Levine)
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion
Message-ID: <844@ima.ISC.COM>
Date: 15 Jan 88 03:23:17 GMT
References: <235@unicom.UUCP>
Reply-To: johnl@ima.UUCP (John R. Levine)
Organization: Not enough to make any difference
Lines: 19
Keywords: bandwidth datapath 128

In article <235@unicom.UUCP> physh@unicom.UUCP writes:
>	It seems to me that one way to get a further increase in
>performance without increasing clock speeds and thus memory and other
>chip costs, would be to leave the processor at 32 bits and increase the
>external data path width to say 128 bits.  Then it may be possible to
>get at least one instruction per fetch.  ...

This is a great idea, but one that has been well known for a long time. The
360/85, just about the first commercial machine with a cache, did exactly that
for the path from core (and I mean core) to the cache. It still seems to be a
standard technique in machines that have separate buses for memory and I/O and
so avoid issues like what a 128 bit path to a serial terminal means.

Speaking of I/O buses, one of the ways that IBM has increased channel speeds
over the years is to move from the original one byte wide System/360 I/O bus
to wider ones.
-- 
John R. Levine, IECC, PO Box 349, Cambridge MA 02238-0349, +1 617 492 3869
{ ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.something
Gary Hart for President -- Let's win one for the zipper.